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PIC18F66K80 FAMILY
DS39977F-page 204
2010-2012 Microchip Technology Inc.
TABLE 12-1:
SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE
REGISTER 12-4:
MDCARL: MODULATION LOW CARRIER CONTROL REGISTER
R/W-0
R/W-x
U-0
R/W-x
MDCLODIS
MDCLPOL
MDCLSYNC
—
MDCL3(1)
MDCL2(1)
MDCL1(1)
MDCL0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
MDCLODIS:
Modulator Low Carrier Output Disable bit
1
= Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register)
is disabled
0
= Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register)
is enabled
bit 6
MDCLPOL:
Modulator Low Carrier Polarity Select bit
1
= Selected low carrier signal is inverted
0
= Selected low carrier signal is not inverted
bit 5
MDCLSYNC:
Modulator Low Carrier Synchronization Enable bit
1
= Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high
time carrier
0
= Modulator output is not synchronized to the low time carrier signal(1)
bit 4
Unimplemented:
Read as ‘0’
bit 3-0
MDCL<3:0>
Modulator Data High Carrier Selection bits(1)
1111
-1001 = Reserved
1000
= CCP5 output (PWM Output mode only)
0111
= CCP4 output (PWM Output mode only)
0110
= CCP3 output (PWM Output mode only)
0101
= CCP2 output (PWM Output mode only)
0100
= ECCP1 output (PWM Output mode only)
0011
= Reference clock module signal
0010
= MDCIN2 port pin
0001
= MDCIN1 port pin
0000
= VSS
Note 1:
Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MDCARH MDCHODIS
MDCHPOL MDCHSYNC
—
MDCH3
MDCH2
MDCH1
MDCH0
MDCARL
MDCLODIS
MDCLPOL
MDCLSYNC
—
MDCL3
MDCL2
MDCL1
MDCL0
MDCON
MDEN
MDOE
MDSLR
MDOPOL
MDO
—
—MDBIT
MDSRC
MDSODIS
—
MDSRC3
MDSRC2
MDSRC1
MDSRC0
PMD2
—
—MODMD
ECANMD
CMP2MD
CMP1MD
Legend:
— = unimplemented, read as ‘0’. Shaded cells are not used in the Data Signal Modulator mode.
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